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Multicore Processors: A Necessity
(Released September 2008)

  by Bryan Schauer  


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Historical Newspapers

News Articles

  1. Resource Management Implementations Will Enable Portability Benefiting Application, Middleware, and System Developers

    Multicore Association Creates Working Group to Develop Multicore Resource Sharing APIs; Multicore Association, PR Newswire 07-15-2008

    EL DORADO HILLS, Calif., July 15 /PRNewswire-USNewswire/ -- The Multicore Association(TM), a global non-profit organization focused on developing standards that help speed time to market for products that involve multicore implementations, has announced the formation of the Multicore Resource Management API working group (MRAPI). The goal of the working group is to develop an industry-standard API that specifies essential application-level resource management capabilities needed to coordinate concurrent access to system resources. The MRAPI specification will complement the consortium's already completed Multicore Communication API (MCAPI), as well as future API specifications.

    Resource management is a crucial capability for high-performance embedded systems, yet there is currently no suitable standard solution in the embedded application space. Standardization will allow multicore processor vendors and third-party tool vendors to take over the resource management aspects and enable system developers to focus their efforts on other critical features of their software that deliver real competitive advantages.

    For full-text documents see ProQuest's eLibrary

  2. Is multicore hype or reality?

    Jack G. Ganssle Embedded Systems Programming 02-01-2008

    For many years, processors and memory evolved more or less in lockstep. Early CPUs like the Z80 required a number of machine cycles to execute even a NOP instruction. At the few-megahertz clock rates then common, processor speeds nicely matched EPROM and SRAM cycle times.

    But for a time, memory speeds increased faster than CPU clock rates. The 8088/6 had a prefetcher to better balance fast memory to a slow processor. A very small (4 to 6 bytes) FIFO isolated the core from a bus interface unit (BIU). The BIU was free to prefetch the most-likely-needed next instruction if the core was busy doing something that didn't need bus activity. The BIU thus helped maintain a reasonable match between CPU and memory speeds.

    Even by the late 1980s, processors were pretty well matched to memory. The 386, which (with the exception of floating-point instructions) has a programmer's model very much like Intel's latest high-end offerings, came out at 16 MHz. The three-cycle NOP instruction thus consumed 188 nsec, which partnered well with most zero wait-state memory devices.

    But clock rates continued to increase while memory speeds started to stagnate. The 386 went to 40 MHz, and the 486 to over 100. Some of the philosophies of the reduced instruction set (RISC) movement, particularly single-clock instruction execution, were adopted by CISC vendors, further exacerbating the mismatch. . . .

    For full-text documents see ProQuest's eLibrary

  3. Multicore Everywhere: The x86 and Beyond

    Scott Gardner looks into the history of multicore CPU architectures, discusses different approaches to multiple cores, and speculates on the future of multic; J. Scott Gardner, 01-09-2006

    Microprocessor architects have often toiled in obscurity as they invent innovative approaches to advance the state of the microprocessor art. Research scientists publish technical papers, and small start-ups add to the Darwinian struggle to find a competitive advantage with clever new architectures.

    However, the world only seems to take notice when a proven architectural approach finds its way into an x86 microprocessor from one of the two leading vendors. The original microprocessor architects often get swept aside as established terminology gets replaced with heavily-marketed buzzwords. Most media help promulgate the public perception that new x86 features started in infancy in a Santa Clara research lab and then emerged, fully-grown and ready to finally lead the computer industry forward.

    The new marketing mania for multicore is the latest example of the belated recognition for a CPU design methodology that already existed before it was popularized by Intel and AMD. Unfortunately, Intel hasn't been able to drive the industry to a consensus on whether "multicore" needs a hyphen. Intel documents show it both ways, and this author is predicting that future generations will not realize the compound word ever had a hyphen. . . . For full-text documents see ProQuest's eLibrary

  4. Mighty Morphing Power Processors

    Otis Port in New York, Business Week 06-06-2005

    Even by the standards of the Lone Star State, the claim by two Texas researchers -- Douglas C. Burger and Stephen W. Keckler -- can seem a trifle grandiose. "We're reinventing the computer," asserts Keckler.

    A glance at their backers, though, dispels some of the skepticism. IBM is working closely with the two University of Texas computer scientists. And the Pentagon's Defense Advanced Research Projects Agency in 2001 handed them $11 million in development funds. Now, IBM is gearing up to manufacture the first prototype of their concept for a radically new computer-brain chip. If it delivers what Burger and Keckler promise, high-tech gurus are betting it will spawn a new family of superchips from Big Blue -- chips capable of crunching a trillion calculations every second.

    Such blistering speed would itself be amazing; it's roughly the oomph of a $50 million supercomputer in 1997. But more impressive, the chip can rewire itself on the fly -- a feat known as reconfigurable computing. With this technology, a future Macintosh from Apple Computer Inc. might rejigger the circuitry on its PowerPC chip and then run software written for Intel Corp.'s microprocessors. Or an iPod music player could turn into a handheld computer -- or detect an incoming call and convert itself into a cell phone. . . .

    For full-text documents see ProQuest's eLibrary

Historical Newspapers
  1. Revolution in Circuitry to Spawn Tiny Computers, TV Receivers
    Ronald Kotulak
    Chicago Tribune, Chicago, Ill.: Feb 27, 1966 pg. 2

    Abstract (Article Summary)

    How would you like to have a personal computer the size of a package of cigarets, a television set no bigger than a deck of cards, and a radio that can be hidden by your thumbnail?

    Original Newspaper Image (PDF)

  2. The computer revolution--when will it be here?
    Los Angeles Times, Los Angeles, Calif.: Nov 15, 1979 pg. 3

    Abstract (Article Summary)

    Ever since personal computers caught the public eye in 1975, there has been increasing speculation about the day when offices, homes and perhaps lives would revolve around the machine.

    Original Newspaper Image (PDF)

  3. When a Computer Joins the Family
    Steven Ditlea
    New York Times, New York, N.Y.: Aug 30, 1979 pg. 2

    Abstract (Article Summary)

    TONY CERRETA, a New Rochelle high school teacher with no previous background in computers, uses his $1,500 Apple II home computer to balance his check book, operate a motion-detecting home burglar alarm, brush up on chess . . . .

    Original Newspaper Image (PDF)

  4. Imitators Are Starting to Go After Market For the Popular IBM Personal Computer
    Richard A. Shaffer
    Wall Street Journal. New York, N.Y.: Nov 4, 1982. pg. 33, 1 pgs

    Abstract (Article Summary)

    The clones are beginning to attack what eventually could become the largest part of the personal-computer market.

    Original Newspaper Image (PDF)

Taken from ProQuest's Historical Newspapers.